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One of the biggest advantages of digital amplifiers is their flexibility in designing multiplexed digital data paths. Because the signal remains in the digital domain before it reaches the speaker, there is more flexibility in signal routing. This flexibility also handles filler selection and / or firmware changes during development and during production . Digital amplifiers have a regular mode called single-ended operation. This paper describes the single-ended design basis and engineering-related trade-off considerations.
Typically, digital amplifiers have a two-stage architecture. As shown in Figure 1 , the pulse width modulation (PWM) processor follows the power stage. A logic-level PWM processor typically receives audio data in IIS format. It performs audio processing and converts pulse code modulation (PCM) data into PWM data. In general, by I
The power stage containing the MOSFET H- bridge is shown in Figure 1 . Here is the use of the MOSFET as a switch so that the +V voltage can be connected across the speaker through the positive / negative direction. Bridge load (BTL) is the standard configuration for most stereo power stages that connect the speaker between two MOSFET half-bridges . Single-ended (SE) means that each speaker is driven by a single MOSFET half-bridge. BTL opposite, the total number of channels is twice the SE; but for a particular output load, SE power of each channel is about 25%. In the SE mode, when the PWM signal is high, the +V voltage connected to the speaker is positive; and when the PWM signal is low, the speaker is grounded.
The single-ended mode of operation of the digital amplifier is shown in Figure 2 , which is not much different from the single-ended operation of a linear audio amplifier. The main difference is that the reconstruction filter ( second-order LC filter ) filters out the high-frequency components of the PWM signal, leaving only the baseband audio signal. Directly supplying the audio signal to the speaker will cause a large DC voltage to be applied to the speaker with a value equal to PVDD/2 . Since the speaker impedance has a large inductive component, this is equivalent to loading a large DC voltage across the inductor , causing the current to rise linearly to a very large value, which can damage the speaker. Therefore, place a large capacitor between the amplifier and the speaker to filter out the DC component. However, this capacitance also causes the lower audio component to attenuate and exhibit a 3dB point at approximately 1/(2Ï€Â·R sp C) , where Rsp is the impedance of the speaker. In order to pass more frequency bandwidth through the speaker, a larger capacitance value capacitor must be used, but at the expense of cost and PCB area.
In the single-ended configuration described above, the audio signal is referenced to ground. In other words, one end of the speaker is grounded. Another way to isolate the DC is to use a split-cap configuration ( as shown in Figure 3 ) , so the reference voltage at the audio signal is now PVDD/2 . From the perspective of communication (AC) , when C sm = C b /2 , there is no difference between Figure 2 and Figure 3 . When inserting the additional capacitance C s to half the rated current is half of the C b and C s equivalent series resistance (ESR) of the double C b, and the audio performance, or no change in temperature.
Figure 1 : Digital Amplifier Data Path with H- Bridge Power Stage
Figure 2 : Single-Ended Digital Amplifier with DC Isolated Capacitor Configuration
Figure 3 : Single-Ended Digital Amplifier with Split Capacitor Configuration
The biggest advantage of the split mode configuration is the increased power supply ripple rejection ratio (PSRR) compared to the isolated capacitor configuration . The curve shown in Figure 4 is the PSRR measurement of TI 's TAS5086/5142 Evaluation Module (EVM) . In this EVM , the power stage of the TAS5142 evaluation board is configured in single-ended mode. Some might wonder if an open-loop single-ended amplifier can have such a high PSRR . The reason is that the voltage change (Î”PVDD) of PVDD is at the midpoint of the split capacitor ( both Î”PVDD/2) , so that the PVDD change through the speaker is cancelled out.
Figure 4 : Single-ended PSRR curve for the TI TAS5086/5142 EVM
The configuration of the SE split mode also needs to address the following two design issues. As described above, after the audio signal reconstruction filter has a size of DC component PVDD / 2 in. If the capacitor C s is ideal, the voltages of both capacitors can be charged to PVDD/2 and no DC component flows through the speaker. However, since the two capacitors are not ideal and there is a deviation, the DC voltage value is not equal to PVDD/2 . Therefore, after power is transmitted to the speaker when the audio signal, there will be a DC voltage through a speaker, causing "snapping" sound. Since the charging time of the separation capacitor is limited by the time constant determined by RC , it causes another related problem. Although this problem does not occur as long as the MOSFET does not generate a switching action before the separation capacitor is fully charged . However, this is difficult to achieve in practical applications, so it will produce a large " squeaky " sound.
The solution to the above two problems is to have a power stage dedicated to fast charging to the half-bridge of PVDD/2 , which is in TAS
In practical applications, the audio performance data of single-ended amplifiers including power-on â€œ åŠˆå•ª â€ , SNR , PSRR , total harmonic distortion + noise (THD+N) is quite good, only slightly inferior to BTL 's audio performance. .
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