The DRV8711 is a highly integrated stepper motor controller that supports microstepping functionality. This feature allows for up to 1/256 microsteps, significantly simplifying the design burden on the MCU. To ensure smooth motor operation and minimize current waveform distortion, the chip includes both fast decay and slow decay modes, as well as additional features like automatic mixed attenuation mode and adaptive blanking time. These functions help improve performance and reduce noise.
In addition to these operational features, the DRV8711 incorporates a comprehensive set of protection mechanisms, such as overcurrent, short-circuit, undervoltage lockout, overtemperature, and pre-driver error protection. A dedicated FAULTn pin provides feedback in case of any fault condition. However, under certain conditions—such as high bus voltage or poor PCB layout—a pre-driver (PDF) error can occur, causing the chip to lock up. This issue can be particularly challenging during system debugging or field deployment.
Figure 1 shows the schematic diagram of the DRV8711 circuit. The pre-driver error is detected internally by the chip. During the off period of the lower MOSFET, the chip performs a 2.2µs timing cycle. If the voltage at the lower gate-source junction exceeds 1V after this period, an error is triggered.
To understand the root cause of the high Cgs voltage observed on the chip side, it’s important to analyze the MOSFET model (as shown in Figure 2). When the upper MOSFET switches, for example, from off to on, the drain voltage of the lower MOSFET rises rapidly. This causes a current Ic to flow through the Cgd capacitor, charging the Cgs capacitance (as illustrated in Figure 3). Although Vgs and Vgd remain relatively stable, the injected current Ic can also couple into the chip via parasitic inductances. This coupling leads to oscillations, which may trigger false pre-driver errors.
Figure 2: Equivalent model of the MOSFET
Figure 3: Ic generation and action process
Based on this analysis, four improvement strategies have been identified:
1. Optimize the PCB layout to minimize the length of the drive loop, thereby reducing the parasitic inductance Lleak.
2. Reduce the value of Ic by adjusting the source current of the upper MOSFET, which lowers the dv/dt. This can be achieved by modifying register 0x6h.
3. Add a resistor Rdriver to suppress oscillations caused by Lleak, thus lowering the monitored voltage at the chip end.
4. Increase the Cgs capacitance to reduce the voltage change caused by the same Ic. This helps stabilize the gate voltage and prevent false triggering.
Among these methods, options 2 and 3 are typically the most effective. However, methods 3 and 4 may reduce the switching speed of the circuit, potentially leading to a "shoot-through" phenomenon. Therefore, when implementing these solutions, it's recommended to adjust the dead time by modifying register 0x0h to 850 ns, ensuring safe and stable operation.
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