The CPU consists of an arithmetic logic unit (ALU) and a control unit. The ALU performs arithmetic operations, logical operations, and bit manipulation. The control unit manages timing and control signals, includes an instruction register, a decoder, an address pointer, and the program counter (PC).
Outside the CPU, there are various peripheral components such as clock circuits, ROM, RAM, timers/counters, parallel I/O ports, serial interfaces, and an interrupt system.
Regarding I/O ports, these are typically General Purpose Input/Output (GPIO) pins, which are implemented as four 8-bit special function registers (SFRs) in the microcontroller.
I/O ports can be configured as either input or output. When used as an output, they have a built-in latch that holds the last written value. For example, after writing a '1', the port will remain at '1' unless an external circuit pulls it down.
In the case of the 51 MCU, P0 requires an external pull-up resistor when used as an output, while P1, P2, and P3 are quasi-bidirectional ports. Some I/O pins can also serve dual functions, such as data or address lines. For instance, P0 is used for both data and address buses, P2 handles high-order address bits, and P3 has secondary functions like serial communication or external interrupts.
It's important to distinguish between reading the pin value and reading the latch. If the port is set to '1' but an external circuit pulls it low, the actual pin might show '0'. To avoid this, when modifying a bit, the MCU reads the latch first, processes it, and then writes back the updated value. Common instructions for bit manipulation include ANL, ORL, XRL, CLR, and SETB.
When reading the pin, you must first write '1' to the port and ensure that the internal driver is turned off so that the actual external voltage level can be read accurately.
A true bidirectional I/O port allows both high and low output levels and exhibits a high-impedance state when unused. However, the P1, P2, and P3 ports in the 51 MCU have internal pull-up resistors, making them quasi-bidirectional. P0 behaves similarly when used as an I/O port without an external pull-up, but when operating in its second function mode, it becomes a full bidirectional port with both transistors active.
Note that sink current capability is generally higher than pull-up current. This is why LEDs are often connected using sink current configurations.
Interrupts are essential for handling real-time events, coordinating fast CPUs with slower peripherals, and enabling efficient task management. Common terms include internal/external interrupts, interrupt service routines (ISR), priority, nesting, and vector addresses.
Interrupts allow the CPU to respond to events like timer overflows, serial communication, or external signals. In the 51 MCU, common sources include external interrupts (INT0, INT1), timer interrupts (T0, T1, T2), and serial communication.
External interrupts can be triggered by either a level or edge signal. Four key registers—TCON, SCON, IP, and IE—control interrupt settings and enable/disable status.
The serial interrupt flag must be cleared manually in software. If a level-triggered interrupt is not reset, the CPU may re-enter the interrupt routine after returning from it.
Interrupt responses are blocked during certain operations, such as executing RETI or accessing IE/IP registers. Only after these instructions can the CPU respond to new interrupts.
Timers and counters are crucial for time-based operations. The 51 MCU has two 16-bit timers, while the 52 version includes a third. These are controlled using the TMOD and TCON registers.
Memory resources in the MCU include internal RAM (typically 128 bytes) and ROM (usually 4KB). RAM stores temporary data during execution, while ROM holds the program code. External memory can be expanded via I/O ports up to 64KB for both RAM and ROM.
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