In today's computing landscape, CPUs and FPGAs have been working in tandem for quite some time. The rise of heterogeneous computing platforms—integrating coprocessors like GPUs, FPGAs, and other intelligent accelerators—has become a major focus in both academic research and industry development. These systems aim to boost computing performance by leveraging the strengths of different hardware components. Let’s explore how CPU+FPGA is being applied in image data storage systems.
With the rapid growth of the mobile internet, images have become a crucial part of daily communication. We are now living in an era where "reading pictures" has become commonplace. According to reports, the global data generated by devices reached 24.3 EB per month in 2019, with 60% of that traffic coming from images. As we move into the "big picture era," where do all these high-quality images come from, and how can we tackle the rising storage costs?
One solution is the WebP lossy compression FPGA acceleration scheme, which enables fast conversion between JPEG and WebP formats. Compared to traditional methods, this approach achieves up to 14 times higher efficiency and supports real-time image retrieval and transmission at higher concurrency levels.
**Using computing power to "replace" storage space**
Currently, common image formats such as JPEG and GIF are widely used, but their limited compression ratios lead to excessive use of server storage resources. To address this, Google introduced the WebP format, which reduces file size significantly while maintaining image quality. WebP is 39.8% smaller than JPEG, 26% smaller than PNG, and 64% smaller than GIF. Using WebP also improves page load speed by 10% and reduces transfer time by 33%.
In China, platforms like Tencent News and QQ Space have started adopting WebP, resulting in a reduction of 9GB in peak bandwidth usage and a decrease of 100ms in image loading delays. However, WebP still requires significant computational power, making it a trade-off between storage and processing power.
Due to its more complex compression algorithm, WebP encoding and decoding demand more computing resources than JPEG, leading to a 10x drop in processing efficiency. Since CPUs aren't optimized for highly parallel tasks, developing efficient hardware acceleration for image encoding and decoding is essential for the widespread adoption of WebP.
**FPGA Accelerated Compression: 14x Performance Boost**
While encoding a single image may seem trivial, the task involves a massive number of concurrent operations. A CPU-based system, limited by clock speed, struggles with such high-volume processing. This is where FPGAs shine. By leveraging parallel computing power, FPGAs can handle multiple tasks simultaneously, effectively acting as several CPUs working in unison.
Inspur has developed a WebP image compression solution using FPGA technology. Based on the industry-leading F10A FPGA card, the solution optimizes the WebP codec through hardware pipeline design and task-level parallelism. The result is a dramatic improvement in performance.
According to Inspur’s measurements, the FPGA-based solution achieves 14 times the efficiency of traditional CPU-based methods. For example, when converting 1,200 JPEG images (2048×1536 resolution), a dual Xeon E5-2690v3 server takes 33.4 seconds to process 35 images per second, while the FPGA solution completes the same task in just 2.39 seconds, handling 502 images per second—a 14.37x speedup.
In today’s digital world, images are everywhere. From e-commerce to social media, image data is growing rapidly, placing heavy pressure on data centers. By accelerating WebP transcoding, Inspur’s FPGA solution not only speeds up image delivery but also reduces the need for extensive storage infrastructure.
Currently, Inspur offers FPGA solutions for WebP compression, Gzip data compression, and ResNet neural networks. Compared to traditional implementations, these solutions offer superior performance per watt. Looking ahead, Inspur plans to expand FPGA-based solutions into areas like deep learning, network acceleration, and storage optimization, aiming to bring these benefits to more industries.
In the future, the combination of CPU and FPGA could become a new standard in heterogeneous computing, especially in data centers and AI-driven applications.
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