Low Noise Amplifier (LNA) is a critical component in various high-sensitivity applications such as radio astronomy, satellite reception, and radar communication systems. Its primary function is to amplify weak incoming signals while minimizing noise, ensuring that the system can effectively demodulate and extract the required information. One of the most important performance metrics for an LNA is the Noise Figure (NF), which directly determines the overall sensitivity of the system. Therefore, the design of the LNA plays a vital role in the performance and reliability of the entire receiver.
In this paper, we focus on the design of a low-noise amplifier for a GPS receiver operating in the frequency range of 1.52 GHz to 1.60 GHz. The key specifications include a noise figure below 1.6 dB, an input VSWR less than 2:1, and an output VSWR less than 1.5:1. These parameters are crucial to ensure efficient signal transmission and minimal distortion.
### 1.1 Device Selection
To achieve the desired low noise performance, we selected the PHEMT GaAsFET transistor, specifically the Agilent ATF-54143. This device is known for its excellent noise performance and high gain, making it ideal for LNA applications. Before designing the amplifier, we created a small-signal model of the transistor, using the provided model from the manufacturer. For the matching network, we employed a reverse-Ï„ configuration composed of lumped inductors and capacitors. To ensure accurate simulation results, we used Murata's models for the components, including the chip inductor LQWl8 and the chip capacitor GRMl8. The inductor LQWl8 has a typical Q value of 80 at 1.6 GHz, which helps maintain low losses and good performance.
### 1.2 DC Bias Design
The DC biasing of the LNA is essential to establish a stable operating point for the transistor. A proper bias ensures optimal noise performance, gain, and linearity. We used a resistor-based passive bias network, consisting of R1 = 60 Ω, R2 = 680 Ω, and R3 = 100 Ω, to set the operating point at Vds = 3.8 V and Ids = 11 mA, as specified in the datasheet. This configuration was chosen due to its simplicity and cost-effectiveness, even though it may not be as temperature-stable as an active bias circuit.
### 1.3 Stability Design
Stability is a fundamental requirement for any amplifier design. To ensure unconditional stability across the operating band, we evaluated the stability using two methods: the K-factor and the μ-factor. Both methods confirmed that the device is stable within the desired frequency range. Additionally, we implemented source degeneration by adding an inductor between the source and ground, which improved the stability without significantly reducing the gain. The simulation results confirmed that the amplifier remains stable over the entire 1.52–1.60 GHz band.
### 1.4 Input and Output Impedance Matching
For the input matching, we used a noise-optimal approach rather than conjugate matching, which helps reduce the noise contribution from the source. The input matching network consists of C4 and L5, which help minimize return loss and improve gain. On the output side, a conjugate match was used with C6 and L7 to maximize power transfer. The design also included RF bypass capacitors and decoupling capacitors to isolate the DC and RF signals properly.
### 1.5 Circuit Optimization
After completing the bias, stability, and matching network designs, we optimized the circuit parameters using ADS software. During optimization, we focused on tuning sensitive parameters and avoiding self-oscillation. We also considered the effects of microstrip lines, vias, and grounding on the final performance. The microstrip line width was calculated using AppCAD software, resulting in a 2.57 mm width for a 50 Ω impedance. Finally, the overall simulation confirmed that the design meets all the required specifications, achieving a noise figure of 1.5 dB and excellent stability across the operating band.
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