Research on a SpaceWire router based on pipeline

In recent years, with the continuous application of SpaceWire bus technology in the field of aerospace, SpaceWire routers have also developed rapidly in theory and technical application. Abroad, the European Space Agency (ESA) has applied a 200 Mb / s radiation-resistant SpaceWire router to ESA ’s space missions. Domestically, the research on SpaceWire routers is still in its infancy, and the designed SpaceWire routers can only reach 100 Mb / s. In order to improve the transmission speed of the router, a SpaceWire router based on pipeline technology is proposed here.

1 SpaceWire router overview

The SpaceWire router is composed of a certain number of link interface units and routing units. The interface unit is mainly responsible for connecting the various SpaceWire contacts, and the routing unit is responsible for the routing exchange of data.

1.1 SpaceWire data link layer interface unit

The SpaceWire data link interface is mainly composed of a connector, LVDS driver, encoder, decoder, state machine, transceiver FIFO, and host interface. Its structure is shown in Figure 1.

The transmitter receives the data from the transmit FIFO, uses DS encoding technology to encode the data and sends it. The receiver is responsible for decoding DS (Din and Sin) signals to generate N-Chars character sequences (data, EOP, EEP), which are transmitted to the host system through the receive FIFO.

The use of FIFO simplifies the interface between the data link and the host system. After the system is reset, both the transmit and receive FIFOs are empty. After the link connection is established, if the FCT is received indicating that the other end of the link is allowed to send data to it, the data written to the transmit FIFO will be sent. When there is still space available in the receive FIFO, the receive FIFO can receive data. The host system reads data from the receive FIFO. Before the FIFO is completely empty or full, the FIFO half-empty or half-full flag will trigger the processor to intervene in the read and write operations of the FIFO. This mechanism can control the data flow through the link, so that the data link interface maintains high-speed data throughput.

The state machine is used to control the overall operation of the interface unit. It provides link initialization, common operations, and error services.

1.2 SpaceWire router unit

In order to simplify the complexity of the SpaceWire-based communication system, it is important to design the SpaceWire routing unit. As shown in Figure 2, the SpaceWire router designed in the figure includes 8 SpaceWire ports, namely 2 external ports, 1 internal configuration port, routing table, control register, status / error register, control logic, non-blocking interaction Switch etc.

Low-latency, wormhole routing and non-blocking switching switches enable data packets to reach any SpaceWire port and external port, or you can directly access any SpaceWire port and external port through the configuration port. The designed SpaceWire port fully supports the SpaceWire standard, providing high-speed, two-way communication. Each external port includes a transmit FIFO and a receive FIFO, which can send and receive characters and packet end flags.

The TIme-code port will be provided along with the counter to facilitate the propagation of TIme-code. When a valid TIme-code arrives at a routing port, it will also be sent to other Spacewire ports, and a TICK_OUT signal will be generated at the Time-code port. The router can use the TICK_IN signal provided by the Time-code port as the operation management of Time-code.

Configuration port can configure any SpaceWire port and external port. It includes registers that can control SpaceWire ports, external ports, and switch switches. The configuration port sets status registers for various ports and switch switches. These registers can be read with the read command of the configuration port to read the status and error information of the router, and the status and error information on some status pins can be selected for output.

The routing table can be accessed through the configuration port. Both logical address port mapping and priority bits can be set in the routing table, which is often used to control groups to adapt to priority arbitration in routing and interactive switches.

1.3 Wormhole routing

The SpaceWire router is designed based on wormhole routing. Wormhole routing is a form of packet routing. The header of each packet contains the address information of the destination. Whenever a packet arrives at the router, it immediately detects the destination address of the packet, and then forwards the packet to the corresponding output port according to the address. If the required output port is in the "free" state, the packet will be forwarded to this output port immediately. At this time, the port will be marked with a "blasy" status flag until the last character of the packet, "EOP", is forwarded through the router.

Wormhole routing is shown in Figure 3. In the figure, a packet is sent from one node and reaches another node through the router. The header is marked black, and the rest is gray. The router is responsible for establishing the connection between the input port and the free output port. When EOP or EEP is detected, the connection is disconnected, the output port is released to the idle state, and it is ready to receive packets from other ports. When the output port is busy, the input port blocks the input packet until it is idle. This is achieved by sending FCTs from nodes far away from the input port. The router does not unblock until the output port is free. The above is the relationship between wormhole routing and flow control.

2 Pipeline-based SpaceWire router

The process of transferring data from the input end to the output end of the SpaceWire router generally needs to go through three stages: first, read the data from the input end and send the target address contained in the packet header to the routing lookup table; again, the routing lookup table Search the target address to determine the output end to which the data packet is sent; Finally, send the data packet to the output end pointed to by the target address. The specific structure is shown in Figure 4.

If there are more than two input terminals in the router to send data to the same output terminal, it will compete for the internal read and write operations of the router. At this time, the router should provide an arbitration mechanism to determine the sending priority. After arbitration, the input that gets the transmission right sends a packet to the output port. In other words, at the same time, there can only be one input terminal in the router to send data. When this input is sent, the other input will send the data. This greatly reduces the working efficiency of the router.

In order to improve the transmission speed of the router, a Spacewire router based on pipeline technology is researched and designed. The key technology is to design a non-blocking parallel switch based on pipeline technology (Figure 5).

The design of the data stream header detection and data rearrangement circuit inside the SpaceWire router is complex and large-scale. In order to simplify the complexity of circuit design, reduce circuit power consumption, and improve the reliability of system operation, for the header detection and data rearrangement circuit of the input data stream, the transaction pipeline technology is used to implement the circuit design. 6 is a block diagram of a circuit scheme for implementing packet header detection and data rearrangement using transaction processing pipeline technology. The experimental results of the circuit design using this design scheme show that the scale of the circuit realized by the pipeline design technology is reduced by 50% compared with the original circuit.

Figure 6 shows the parallel switching architecture. The FPGA is used to implement K M × M bufferless crossbar switches as switching modules. This architecture is composed of M input shared memory modules, K crossbar switches, and M output shared memory modules. Each input / output shared memory module has V external line interfaces and is connected to all crossbar switches at the same time.

The input shared memory module contains (M * V) VOQs (virtual output queues), which store cells output to different destination ports. The output shared memory module contains V output queues to save cells waiting for output. In each arbitration cycle, the input port randomly selects M queues from (M * V) VOQ queues and submits a scheduling request to the switch. The switch provides services for each queue in a polling manner, and feeds back authorization information to the input port according to the scheduling result. The VOQ queue head cell specified by the authorization information directly reaches the output queue through the exchange switch, and after packet reassembly and other processing is completed, it is sent to the external link. To avoid buffer overflow at the output, a backpressure mechanism can be used to prevent the input from sending excessive cells in time.

When multiple inputs send data to one output, pipeline technology is used in the switch to allow multiple inputs to send data to the output in a time-sharing manner. You can also copy a routing lookup table at each input, so that no arbitration mechanism is needed. When the data stream enters the input terminal, it looks up the routing table according to the packet header address, determines the output terminal to be sent, and then sends it. When multiple input terminals transmit, a time token is assigned to each input terminal. When the time token is valid, it is transmitted. When the time token is invalid, the transmission is stopped until all data is transmitted. The distribution of time tokens is controlled by routing algorithms. The basic idea is to use the pipeline to distribute the time tokens to each input node in turn, and to optimize the routing algorithm according to specific circumstances. This work is currently in progress. The SpaceWire router designed based on this pipeline technology will reach 200 Mb / s. Therefore, the data transmission of the SpaceWire network is faster, and the simultaneous access from each input end to the output end can also be achieved.

3 Conclusion

The basic principle of the SpaceWire router is introduced, and the research of a SpaceWire router based on pipeline technology is emphasized. The key technology is to use FPGA to design a switch based on pipeline technology. The SpaceWire router meets the future development needs of the aerospace industry, so the speed of the spaceWire router is a very critical indicator. This article introduces a method to improve the speed of Spacewire router, which has high research value. This research is currently being implemented.

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